In the development of serial data communication channels, it is necessary for compliance testing to measure a bit-error-rate (BER) and further to determine any sources of degradation of BER in the channel. One of the most important sources of BER degradation is jitter. Therefore it is important to understand the jitter contribution to the BER degradation.
Many different measurement solutions exist for measuring jitter and BER. These consist of a bit error rate tester (BERT), a time interval analyzer (TIA) and the digital oscilloscope (DSO). The DSO solutions include both the equivalent time or so-called sampling oscilloscope and the real-time oscilloscope.
The real-time oscilloscope is rapidly becoming the instrument of choice for jitter testing. Such a real-time scope measures jitter in many ways. The basic idea is to capture a long record of a serial data signal, extract a clock waveform using a digital phase-locked-loop (PLL) and measure the difference between the clock edge and the data edge at the boundaries of a unit interval (UI). The measurement of this difference for each data bit is called the time interval error (TIE). The measurement and analysis of multiple values of TIE for a waveform leads to a characterization of jitter. This measured jitter may further comprise many components, including both random and deterministic jitter, bounded and unbounded jitter, periodic jitter, intersymbol interference (ISI) induced jitter etc. Of particular concern is the random unbounded jitter, typically assumed and measured to be Gaussian in nature. This is because of the industry-accepted standard relationship of total jitter to the random and deterministic jitter:Tj=Dj+14·Rj
In this equation, Dj is the peak-peak deterministic (bounded) jitter and Rj is the standard deviation of the assumed Gaussian distributed (unbounded) random jitter. The factor of 14 is used to determine the peak-peak jitter. The equation is valid for a BER of 1 error per 1012 transmitted bits. The Tj is the maximum eye closure due to jitter for this number of bits and it must not exceed the unit interval.
In measurement instruments, the classification of jitter, especially between deterministic and random jitter is very important because any inadvertent classification of jitter as random or deterministic involves the above-noted factor of 14. Furthermore, random jitter is most often a function of clock generation, so for clock component manufacturers manufacturing clocks with very low Rj, it is important that any measurement instrument can measure very low values of Rj accurately.
Regarding the real-time oscilloscope as a jitter measurement instrument, one figure of merit is the jitter noise floor. The jitter noise floor is defined as the lowest value of Rj that the scope will measure when an input signal is applied with zero Rj. Typically, the Rj value calculated will be the quadrature addition of the jitter noise floor of the oscilloscope and the actual Rj present in the device under test.
It is important that the jitter noise floor of the measurement instrument be as low as possible.
Sources of error that lead to increased jitter noise floor in the oscilloscope are vertical noise, phase noise and timebase stability of the internal oscilloscope clock, and timing errors of analog-to-digital converters (ADCs) used to digitize the waveform. When time interleaved ADCs are utilized to digitize the waveform, the timing errors are due to an effect called interleave error.
Many efforts have been made to minimize all of these effects and therefore to lower their effect on jitter measurements. With regard to interleave error, the prior art has typically dealt with this by designs that calibrate the ADC timing in the scope (see Meadows, U.S. Pat. No. 4,962,380, Jeng, U.S. Pat. No. 4,763,105 and Schachner et al., U.S. Pat. No. 6,269,317). These methods address only the measurement and adjustment of hardware means for adjusting timing relationships that do not vary with frequency and is a good first order calibration. Unfortunately, interleave error usually, to some extent, varies with frequency. Other methods have been utilized to correct for the error utilizing digital signal processing methods (see Apple et al. U.S. Pat. No. 5,239,299, Pupalaikis U.S. Pat. No. 6,567,030, and Pupalaikis U.S. Pat. No. 6,819,279). These methods, although precise, will still have some residual error. Other methods attempt to reduce the symptoms of ADC interleave error (such as Mueller et al., U.S. patent application Ser. No. 11/280,493), but these methods are not exact.
All of the prior art utilized to correct for interleave error result in improvements of the effect on the jitter noise floor due to interleave error, but a method is needed that directly compensates for increased jitter noise floor due to the effect of interleave error, or possibly the residual interleave error when any of this prior art is utilized.